The present invention relates to memory systems and, more specifically, to an interface scheduler for a distributed memory system.
A distributed memory system includes a card connected to a host processor, also referred to as a host. The card includes dynamic random-access memory (DRAM) used for data storage by the host, as well as an Address and Command chip (AC), which accepts fetch and store commands over a link from the host and schedules those commands to be executed on the DRAM memory. The card additionally includes a set of Data Chips (DCs), which receive store data from the host over a link between the DCs and the host. The DCs hold the store data in a buffer until the AC schedules the store data to be stored to the DRAM. Likewise, the DCs receive, from the DRAM, fetch data from fetch operations scheduled by the AC, and the DCs send that fetch data over a high-speed serial (HSS) link to the host.
Unlike in a traditional direct attached memory system, where the host decides when each operation is to be executed on the DRAM, in a distributed memory system, the AC controls the order and timing of every DRAM operation. Therefore, the AC must provide the following communications: (1) On a fetch operation, the AC notifies the host of which fetch operation corresponds to arriving data. This notification occurs as a read response command, also referred to as a read response, sent to the host over an HSS link. (2) On a fetch operation, the AC also notifies the DCs of when and on which memory port fetch data will arrive. This notification is sent over a broadcast bus, referred to as data buffer control/communication (BCOM), from the AC to the DCs. (3) On a store operation, the AC notifies the DCs via the BCOM that data is arriving from the host, for which operation that data is arriving, and where to hold that data in its store buffers. At an undetermined time later, the AC actually schedules that store operation for execution on the DRAMs. The AC then notifies the DCs of what data to send to the DRAMs from the store buffers via the BCOM, and the AC informs the host via the HSS link that the store has completed via the HSS link.
Certain of these AC communications are sent a specific number of memory cycles before the data for the respective operations is set to arrive. For instance, a fixed number of cycles occurs between an AC command sent to a DC over the BCOM and the data arriving to the DC from the host for a store operation, and another fixed number of cycles occurs between an AC command sent to the host notifying the host that data is arriving for a fetch operation and the data arriving from the DCs for that fetch operation.